The present invention relates to the designing a semiconductor integrated circuit, and more particularly, to the designing of power supply wiring of a semiconductor integrated circuit.
In the prior art, the enlargement and higher speed of an LSI has increased the ratio of the area occupied by a power supply in a semiconductor integrated circuit. It is thus required that power supply wiring be optimized to guarantee the reliability of the power supply and reduce the affect on the operation of a semiconductor integrated circuit device.
Two examples of methods for designing a power supply of an LSI are described below.
(1) In the first method, a power supply wiring having sufficient power supply capacity is designed without taking into consideration the power consumption of the logic circuit. In this case, the power supply wiring is not changed even if the logic circuit is modified. After the layout of a semiconductor integrated circuit (LSI) is completed, it is normally determined whether to modify the logic circuit based on the results of various verifications, such as timing verification and crosstalk verification.
(2) In the second method, the layout of a power supply wiring is changed after the logic circuit is modified, and power supply verification is conducted on the modified layout. When it is determined from the result of the verification that the characteristic must be improved, the power supply wiring is laid out again (Japanese Laid-Open Patent Publication No. 2000-20576).
However, the first method results in redundant power supply wiring and increases the area of the semiconductor integrated circuit. Further, if the power supply wiring does not have sufficient power supply capacity, a voltage drop would lead to insufficient power supply voltage. In such a case, the same operations as those performed during a circuit simulation may not be obtained.
In the second method, when the logic circuit is modified, the layout must always be changed and the power supply verification (power supply network analysis) must always be performed. The layout modification and the power supply network analysis increase design costs. Further, when the logic circuit is modified to adjust timings or to cope with crosstalk, a cell, such as a gate, is newly added to the logic circuit. The layout of the power supply wiring is changed in accordance with the modification of the logic circuit. The layout modification varies the characteristic of the semiconductor integrated circuit. Thus, to improve the characteristic of the semiconductor integrated circuit having the new layout subsequent to the modification, timings must be adjusted again and crosstalk must be coped with again. As a result, there would be no meaning to the addition of the cell when modifying the first logic circuit. Such modification of the logic circuit, change in the layout of the power supply wiring, and the power supply verification are repeated the number of times. This increases designing costs.